- Date: July, 2021
- Members: Frontier System Laboratory, Center for Advanced Computer Systems, Institute of Computing Technology, Chinese Academy of Sciences, Beijing Institute of Open Source Chip, etc.
- Partners: PengCheng Laboratory, Shenzhen University of Advanced Technology, Hong Kong University of Science and Technology (Guangzhou), etc.
- Slogan: (Build an) Ecosystem for Collaborative and Open Silicon
- Goal: We build open-source chip design solutions and their supporting technology ecosystem. By using "open source" to innovate chip design methods, we aim to lower the threshold of chip design with open source and empower thousands of industries.
An open-source chip design automation solution that brings synthesis, physical design, timing, verification, and layout viewing into one RTL-to-GDS flow.
Designed for: chip designers who need a reproducible command-line flow or a Python API for automation.
Yosys, ECC-DreamPlace, ECC-Tools, and KLayout
CLI, Python API, reports, and signoff export
A large-scale, open, public-welfare chip and system talent-training initiative in which students learn to design, tape out, and bring up their own processor chips.
Designed for: students and self-directed learners who want hands-on, full-stack processor design experience.
Processor RTL, SoC integration, and system software
Verification, tapeout, and chip bring-up
An open-source RISC-V SoC platform spanning SystemVerilog RTL, firmware, reproducible verification, and release artifacts.
Designed for: developers building configurable RISC-V systems across simulation, FPGA, and ASIC targets.
RTL, firmware, HAL, applications, and release tooling
Simulation, synthesis, timing, and structured artifacts
A 55nm CMOS open-source process design kit with design rules, device models, standard cells, and physical-design collateral.
Designed for: universities, researchers, and open-source silicon teams exploring physical design and test tapeouts.
Technology files, cells, and implementation collateral
Design rules and physical verification support
An open knowledge platform for chip manuals, board references, SDKs, development tools, and application examples built around ECOS chips.
Designed for: embedded developers turning open-source silicon into working boards, prototypes, and applications.
SDKs, tools, manuals, and board documentation
Reference projects for real hardware use cases
A one-stop RTL-to-chip design solution that integrates open-source IP, the ECC toolchain, and accessible PDKs in a unified desktop environment.
Designed for: researchers, engineers, and students who want a visual workspace and an FPGA-like ASIC design experience.
Manage projects and run RTL-to-GDS from the GUI
Composable IP, ECC, and ICsprout55 integration
A cloud platform for configurable IP, MPW aggregation, and tapeout services.
Designed for: teams looking for a guided path from reusable silicon components to a submitted tapeout project.
Discover and configure reusable chip IP
Project submission and MPW aggregation
- [FSiC 2026] ECOS Studio: an RTL-to-chip silicon design solution with open-source EDA, IP, and PDK
- [FSiC 2026] "One Student One Chip" initiative: learn to build RISC-V chips from scratch with MOOC
- [FSiC 2025] "One Student One Chip" initiative: Learn to build RISC-V chips from scratch with MOOC
- [FSiC 2025] Making Open Silicon Design Everywhere: Using Cloud-based Open Agile EDA Platform